Reduction of machining load in "the finishing process" of SiC wafer surface grinding
The production of compound semiconductor wafers, which are used as substrates for power devices, is expected to grow steadily in the trend toward power saving in a low-carbon society. The key to this growth is the processing cost of wafers, and in the finishing process of surface grinding (fine grinding), it is necessary to reduce the machining load and improve the surface roughness.
Our porous vitrified bond wheel "VEGA" can increase the abrasive grain tip pressure and maintain a non-slip grinding condition, making it possible to greatly reduce the wheel axial current during machining, thus maintaining a low wheel wear rate. It also reduces the risk of deep damage to the work material, cracking, and chipping, and achieves good surface roughness.
“VEGA” Porous vitrified bond wheel for compound semiconductor wafers
Bond : Porous vitrified bond
Grain size : #4000～#12000
SiC, GaN, GaAs, LT/LN
■Higher surface roughness is realized by the combination of ultra-fine diamond abrasive grains and vitrified bonds of large and fine porous combination structure.
■Spontaneous blade generation is realized and cutting quality is maintained by bonds that can make ultrafine shredding.
■Stable high-quality surface and low processing cost can be realized.